Counter Command Register (Cnt_Command) - Analog Devices ADSP-BF506F Hardware Reference Manual

Counter Status (CNT_STATUS) Register
15
0
CZMZIE
(Counter zeroed by zero marker) (W1C)
CZMEII
(Zero marker error interrupt) (W1C)
CZMII
(CZM pin interrupt/ Push-button interrupt) (W1C)
CZEROII
(CNT_COUNTER counts to zero interrupt) (W1C)
COV15II
(Bit 15 overflow interrupt) (W1C)
Figure 13-7. Counter Status Register

Counter Command Register (CNT_COMMAND)

The
CNT_COMMAND
ures the GP counter, enabling operations such as zeroing a counter register
and copying or swapping boundary registers. These actions are taken by
writing a "one" to the appropriate bit.
Read operations from this register will not return meaningful values, with
the exception of the
been set by software before, but no zero marker event has been detected on
the pin yet. Refer to
CZM
page 13-9 for more details.
The
CNT_COUNTER
by writing a "one" to the
fields. In addition to clearing registers,
registers to be modified in a number of ways. The current counter value in
can be captured and loaded into either of the two boundary
CNT_COUNT
ADSP-BF50x Blackfin Processor Hardware Reference
14 13 12 11 10 9 8 7
0 0 0 0 0 0 0 0
For all bits:
0 = No Interrupt pending
1 = Interrupt pending
register (shown in
bit, where a "1" indicates that the bit has
W1ZONCE
"Zero Marker (Push Button) Operation" on
, and
CNT_MIN CNT_MAX
W1LCNT_ZERO
General-Purpose Counter
6 5 4 3 2 1 0
0 0 0 0 0 0 0
ICII
(Illegal Gray/binary code
interrupt) (W1C)
UCII
(Upcount interrupt)
DCII
(Downcount interrupt) (W1C)
MINCII
(Min interrupt) (W1C)
MAXCII
(Max interrupt) (W1C)
COV31II
(Bit 31 overflow
interrupt) (W1C)
Figure 13-8 on page
registers can be initialized to zero
, and
W1LMIN_ZERO
allows the boundary
CNT_COMMAND
Reset = 0x0000
13-23) config-
W1LMAX_ZERO
13-21