Analog Devices ADSP-BF506F Hardware Reference Manual page 550

Overview
The PWM generator is capable of operating in two distinct modes:
• Single-Update Mode. In single-update mode, duty cycle values are
programmable only once per PWM period; resultant PWM pat-
terns are symmetrical about the mid-point of the PWM period.
• Double-Update Mode. In double-update mode, a second updating
of the PWM registers is implemented at the midpoint of the PWM
period. In double-update mode, it is possible to produce asymmet-
rical PWM patterns that produce lower harmonic distortion in
three-phase PWM inverters. This technique also permits
closed-loop controllers to change the average voltage applied to the
machine windings at a faster rate, thus permitting faster
closed-loop bandwidths to be achieved.
The operating mode of the PWM block (single- or double-update mode)
is selected by the
to 1 selects double-update mode, and 0 selects single-update mode.
The PWM generator can provide an internal synchronization pulse on the
pin that is synchronized to the PWM switching frequency. In
PWM_SYNC
single-update mode, a
PWM period. In double-update mode, an additional
also produced at the midpoint of each PWM period. The width of the
pulse is programmable through the
PWM_SYNC
The PWM generator can also accept an external synchronization pulse on
the pin. External synchronization is selected by setting the
PWM_SYNC
bit in the
PWM_EXTSYNC
be synchronized to the internal system clock, which is selected by setting
the
PWM_SYNCSEL
tion pulse from the chip pin is asynchronous to the internal system clock
(typical case), the external
should be synchronized. If the
PWM on the same chip controlled by the same system clock, the
can usually be considered synchronous. Synchronization logic will add
14-6
bit in the
PWM_DBL
pulse is produced at the start of each
PWM_SYNC
register. The
PWM_CTRL
bit of the
PWM_CTRL
PWM_SYNC
PWM_SYNC
ADSP-BF50x Blackfin Processor Hardware Reference
register. Setting
PWM_CTRL
PWM_SYNC
PWM_SYNCWT
PWM_SYNC
register. If the external synchroniza-
is considered asynchronous and
is actually received from another
PWM_DBL
pulse is
register.
input timing can
PWM_SYNC