Analog Devices ADSP-BF506F Hardware Reference Manual page 257

Adsp-bf50x blackfin processor
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When
DMAx_CONFIG
recognizes this as the special startup condition that occurs when starting
DMA for the first time on this channel or after the engine has been
stopped (
FLOW
When the descriptor fetch is complete and
tor element that was read into
point, the direct write to
,
,
WDSIZE
DI_EN
value in the descriptor read from memory, while these field values
DMACFG
initially written to the
As
Figure 7-1
and
determine the course of the DMA setup process. The
DMAx_CONFIG
value determines whether to load more current registers from descriptor
elements in memory, while the
elements to fetch before starting DMA. DMA registers not included in the
descriptor are not modified from their prior values.
If the
value specifies small or large descriptor list modes, the
FLOW
DMAx_NEXT_DESC_PTR
new descriptor elements from memory are performed, indexed by
DMAx_CURR_DESC_PTR
and/or
is part of the descriptor, then these values are loaded into
NDPH
DMAx_NEXT_DESC_PTR
using
DMAx_CURR_DESC_PTR
DMAx_CURR_DESC_PTR
end of the descriptor.
If neither
NDPH
array mode,
FLOW
DMAx_CURR_DESC_PTR
begins with the value in
If
is not part of the descriptor, the previous
DMACFG
(as written by MMR access at startup) control the work unit operation. If
ADSP-BF50x Blackfin Processor Hardware Reference
is written directly by software, the DMA controller
= 0).
DMAx_CONFIG
DMAx_CONFIG
,
, and
DI_SEL
SYNC
DMAx_CONFIG
Figure 7-2
show, at startup the
NDSIZE
is copied into
, which is incremented after each fetch. If
, but the fetch of the current descriptor continues
. After completion of the descriptor fetch,
points to the next 16-bit word in memory past the
nor
are part of the descriptor (that is, in descriptor
NDPL
= 4), then the transfer from
does not occur. Instead, descriptor fetch indexing
DMAx_CURR_DESC_PTR
Direct Memory Access
= 1, the
DMAEN
assumes control. Before this
had control. In other words, the
fields will be taken from the
DMA2D
register are ignored.
FLOW
bits detail how many descriptor
DMAx_CURR_DESC_PTR
/
NDPH
NDPL
.
DMAx_CONFIG
descrip-
DMACFG
and
bits in
NDSIZE
FLOW
. Then, fetches of
NDPL
into
settings
7-21

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