Programming Model
and force the DMA controller to fetch the next descriptor. To accomplish
this, the software writes a value with the
ues in the
FLOW
descriptor is fetched if
ation, the
NDSIZE
overwrite the configuration register immediately.
One possible procedure is:
1. Write to
2. Write to
FLOW
NDSIZE
DI_EN
DMAEN
3. Automatically fetched
FLOW
NDSIZE
SYNC
DI_EN
DMAEN
4. In the interrupt routine, repeat step 2. The
updated by the descriptor fetch.
To avoid polling of the
memory read DMAs (DMA transmit or MDMA source).
7-62
and
fields into the configuration register. The next
NDSIZE
equals 0x4, 0x6, or 0x7. In this mode of oper-
FLOW
field should at least span up to the
DMAx_NEXT_DESC_PTR
with
DMAx_CONFIG
= 0x8
0xA
= 0
= 1
DMACFG
= 0x0
= 0x0
= 1 (for transmitting DMAs only)
= 1
= 1
DMA_RUN
ADSP-BF50x Blackfin Processor Hardware Reference
bit set and with proper val-
DMAEN
DMACFG
has
DMAx_NEXT_DESC_PTR
bit, set the
SYNC
field to
is
bit in case of
Need help?
Do you have a question about the ADSP-BF506F and is the answer not in the manual?