Amc Programming Model - Analog Devices ADSP-BF506F Hardware Reference Manual

One case where contention can occur is a read followed by a write to the
same memory space. In this case, the data bus drivers can potentially con-
tend with those of the memory device addressed by the read.
To avoid contention, program the turnaround time (bank transition time)
appropriately in the asynchronous memory bank control registers. This
feature allows software to set the number of clock cycles between these
types of accesses on a bank-by-bank basis. Minimally, the EBIU provides
one cycle for the transition to occur.

AMC Programming Model

The asynchronous memory global control register (
ures global aspects of the controller. It contains bank enables and other
information as described in this section. This register should not be
programmed while the AMC is in use. The
the last control register written to when configuring the processor to
access external memory-mapped asynchronous devices.

The AMC interface is used to access the internal flash memory on
ADSP-BF50x processors containing a flash. For more information,
see "Internal Flash Memory" on page
Additional information for the
• Asynchronous memory clock enable (AMCKEN)
The external clock signal (
the system clock signal SCLK, can be enabled by setting the
bit in the
set the
AMCKEN
ADSP-BF50x Blackfin Processor Hardware Reference
EBIU_AMGCTL
CLKOUT
register. In systems that do not use
EBIU_AMGCTL
bit to 0.
External Bus Interface Unit
EBIU_AMGCTL
register should be
EBIU_AMGCTL
6-1.
register bits includes:
), which is an inverted version of
) config-
AMCKEN
,
CLKOUT
5-7