General-Purpose I/O Modules - Analog Devices ADSP-BF506F Hardware Reference Manual


By default all peripheral pins are configured as inputs after reset.
port F, port G, and port H pins are in GPIO mode. However,
GPIO input drivers are disabled to minimize power consumption
and any need of external pulling resistors.
When the control bit in the function enable registers (
the pin is set to its peripheral functionality and is no longer controlled by
the GPIO module. However, the GPIO module can still sense the state of
the pin. When using a particular peripheral interface, pins required for the
peripheral must be individually enabled. Keep the related function enable
bit cleared if a signal provided by the peripheral is not required by your
application. This allows it to be used in GPIO mode.

General-Purpose I/O Modules

The processor supports 35 bidirectional or general-purpose I/O (GPIO)
signals. These 35 GPIOs are managed by three different GPIO modules,
which are functionally identical. One is associated with port F, one with
port G, and one with port H. Port F and port G each consist of 16 GPIOs
( and
PF15–0 PG15–0
( ).
PH7-0
Each GPIO can be individually configured as either an input or an output
by using the GPIO direction registers (
When configured as output, the GPIO data registers (
and ) can be directly written to specify the state of the GPIOs.
PORTHIO
The GPIO direction registers are read-write registers with each bit posi-
tion corresponding to a particular GPIO. A logic 1 configures a GPIO as
an output, driving the state contained in the GPIO data register if the
peripheral function is not enabled by the function enable registers. A logic
0 configures a GPIO as an input.
ADSP-BF50x Blackfin Processor Hardware Reference
), respectively. Port H consists of three GPIOs
General-Purpose Ports
PORTx_FER
).
PORTxIO_DIR
PORTFIO
) is set,
, ,
PORTGIO
9-13