Uartx_Lcr Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

UART Registers

UARTx_LCR Registers

The line control (
format of received and transmitted character frames.
UART Line Control Registers (UARTx_LCR)
15 14 13 12 11 10
For memory- 0 0
mapped
addresses,
see
SB (Set Break)
0 - No force
1 - Force TX pin to 0
STP (Stick Parity)
Forces parity to defined value if set and PEN = 1
EPS = 0, parity transmitted and checked as 1
EPS = 1, parity transmitted and checked as 0
EPS (Even Parity Select)
0 - Odd parity when PEN = 1 and STP = 0
1 - Even parity
Figure 15-8. UART Line Control Registers
Table 15-4. UART Line Control Register Memory-Mapped Addresses
Register Name
UART0_LCR
UART1_LCR
The 2-bit
WLS
UART word consists of 5, 6, 7 or 8 data bits.
15-28
) registers, shown in
UARTx_LCR
9 8 7
0 0 0 0 0 0 0
Memory-Mapped Address
0xFFC0 040C
0xFFC0 200C
field determines whether the transmitted and received
ADSP-BF50x Blackfin Processor Hardware Reference
Figure
6 5 4 3 2 1 0
0 0 0 0 0 0 0
15-8, control the
Reset = 0x0000
WLS[1:0] (Word Length
Select)
00 - 5-bit word
01 - 6-bit word
10 - 7-bit word
11 - 8-bit word
STB (Stop Bits)
0 - 1 stop bit
1 - 2 stop bits for non-5-bit
word length or 1 1/2 stop
bits for 5-bit word length
PEN (Parity Enable)
0 - Parity not transmitted or
checked
1 - Transmit and check
parity