Internal Memory Interfaces; Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

EBIU Overview
Note that—because the EBIU memory-interface signals do not come out
to package pins—no external memory devices can be supported by the
EBIU in ADSP-BF50x Blackfin processors.

Internal Memory Interfaces

The EBIU functions as a slave on three buses internal to the processor:
• External Access Bus (EAB), mastered by the core memory manage-
ment unit on behalf of external bus requests from the core
• DMA External Bus (DEB), mastered by the DMA controller on
behalf of external bus requests from any DMA channel
• Peripheral Access Bus (PAB), mastered by the core on behalf of sys-
tem MMR requests from the core
These are synchronous interfaces, clocked by
EAB provides access to external memory.
The peripheral access bus (PAB) is used only to access the mem-
ory-mapped control and status registers of the EBIU. It does not need to
arbitrate with, nor take access cycles from, the EAB bus.
The External Bus Controller (EBC) logic must arbitrate access requests for
external memory coming from the EAB and DEB buses. Transactions
from the core have priority over DMA accesses in most circumstances.
However, if the DMA controller detects an excessive backup of transac-
tions, it can request its priority to be temporarily raised above the core.

Registers

The EBIU has a number of control and status registers. They include:
• Asynchronous memory global control register (
• Asynchronous memory bank control register (
5-4 ADSP-BF50x Blackfin Processor Hardware Reference
, as is the EBIU. The
SCLK
EBIU_AMGCTL
EBIU_AMBCTL
)
)