Handshaked Memory Dma Operation - Analog Devices ADSP-BF506F Hardware Reference Manual

senting more data items than the maximum work unit size that the
peripheral will encounter. For example,
DMAx_CURR_Y_COUNT
1-D work units up to 65,535 data items and 2-D work units up to
4,294,967,295 data items.

Handshaked Memory DMA Operation

Handshaked memory DMA operation is not available for all products.
Refer to "Unique Information for the ADSP-BF50x Processor" on
page 7-103 to determine whether this feature applies to this product.
Each input has its own set of control and status registers. Hand-
DMARx
shake operation for MDMA0 is enabled by the
HMDMA0_CONTROL
register enables handshake mode for MDMA1.
It is important to understand that the handshake hardware works com-
pletely independently from the descriptor and autobuffer capabilities of
the MDMA, allowing most flexible combinations of logical data organiza-
tion vs. data portioning as required by FIFO depths, for example. If,
however, the connected device requires certain behavior of the address
lines, these must be controlled by traditional DMA setup.

The HMDMA unit controls only the destination (memory write)
channel of the memory DMA. The source channel (memory-read
side) fills the 8-deep DMA buffers immediately after the receive
side is enabled and issues eight read commands.
The
HMDMAx_BCINIT
formed upon every DMA request. If set to one, the peripheral can time
every individual data transfer. If greater than one, the peripheral must
have sufficient buffer size to provide or consume the number of words
programmed. Once the transfer has been requested, no further handshake
can hold off the DMA from transferring the entire block, except by
stalling the EBIU accesses by the
ADSP-BF50x Blackfin Processor Hardware Reference
values of 0 allow the channel to operate properly on
register. Similarly, the
registers control how many data transfers are per-
ARDY
Direct Memory Access
DMAx_CURR_X_COUNT
bit in the
HMDMAEN
bit in the
HMDMAEN
signal. Nevertheless, the peripheral
/
HMDMA1_CONTROL
7-37