Analog Devices ADSP-BF506F Hardware Reference Manual page 617

when it is not empty overwrites the register with the new value and the
previous character is never transmitted.
The flag signals when new data is available in
DR
cleared automatically when the processor reads from
when it is not full returns the previously received value. When
UARTx_RBR
is not read in time, an overrun condition protects the already
UARTx_RBR
received data from being overwritten by new data until the
cleared by software. Only the content of the
ten in the overrun case.
The bit can be interrogated to see whether any transmission is ongo-
TEMT
ing. The bit's sticky counterpart
TEMT
has drained and can trigger a status interrupt, if required.
With interrupts disabled, these status flags can be polled to determine
when data is ready to move. Note that because polling is processor inten-
sive, it is not typically used in real-time signal processing environments.
Since read operations from
ent software threads can interrogate these registers without mutual
impacts. Polling the
is an alternate method of operation to consider. Software can
SIC_MASKx
write up to two words into the
UART clock. As soon as the
Alternatively, UART writes and reads can be accomplished by interrupt
service routines (ISRs). Separate interrupt lines are provided for UART
TX, UARTxRX, and UART status. The independent interrupts can be
enabled individually by the
pair. The
UCEN
The ISRs can evaluate the status bits in the
isters to determine the signalling interrupt source. Interrupts also must be
assigned and unmasked by the processor's interrupt controller. The ISRs
must clear the interrupt latches explicitly. See
page 15-41.
ADSP-BF50x Blackfin Processor Hardware Reference
UARTx_LSR
register without enabling the interrupts by
SIC_ISRx
UARTx_THR
UCEN
UARTx_IER_SET
bit must be set to enable UART transmit interrupts.
UART Port Controllers
UARTx_RBR
register can be overwrit-
RSR
tells whether the transmit buffer
TFI
registers have no side effects, differ-
register before enabling the
bit is set, those two words are sent.
and
UARTx_IER_CLEAR
UARTx_LSR
Figure 15-15 on
. This flag is
. Reading
UARTx_RBR
bit is
OE
register
and reg-
UARTx_MSR
15-23