Analog Devices ADSP-BF506F Hardware Reference Manual page 548

Overview
The PWM Controller is driven by a clock, whose period is t
PWM generator produces three pairs (
, and
PWM_CH PWM_CL
are three high-side drive signals (
low-side drive signals (
generated PWM signals may be programmed by the
the register to generate active high or active low PWM patterns.
PWM_CTRL
The switching frequency and dead time of the generated PWM patterns
are programmable via the
duty-cycle control registers (
trol the duty cycles of the three pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled via sepa-
rate output enable bits of the
bits of the
PWM_SEG
nals of a PWM pair for easy control of ECMs or BDCMs. In crossover
mode, the PWM signal destined for the high-side switch is diverted to the
complementary low-side output, and the signal destined for the low-side
switch is diverted to the corresponding high-side output signal for ECM
or BDCM modes of operation. A typical configuration for these types of
motors is shown in
In common three-phase inverters, it is necessary to insert a so-called "dead
time" between turning off one switch and turning on the other switch in
the same leg, to prevent shoot-through. This dead time is inserted by an
emergency dead-time insertion circuit, which enforces a dead time defined
by the register between the high- and low-side drive signals of each
PWM_DT
PWM channel. This ensures that the correct dead time occurs at the
power inverter.
In many applications, there is a need to provide an isolation barrier in the
gate-drive circuits that turn on the power devices of the inverter. In gen-
eral, there are two common isolation techniques: optical isolation using
opto-isolators, and transformer isolation using pulse transformers. The
PWM Controller permits the mixing of the output PWM signals with a
14-4
) of PWM signals on the six PWM output pins. There
PWM_AH
,
PWM_AL PWM_BL
and
PWM_TM
,
PWM_CHA
PWM_SEG
register permit independent crossover of the two sig-
Figure 14-2.
ADSP-BF50x Blackfin Processor Hardware Reference
, ,
PWM_AH PWM_AL PWM_BH
, , and
PWM_BH PWM_CH
, and ). The polarity of the
PWM_CL
PWM_POLARITY
registers. In addition, three
PWM_DT
, and
PWM_CHB PWM_CHC
register. In addition, three control
. The
SCLK
, ,
PWM_BL
) and three
bit of
) directly con-