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System Interrupt Assignment (SIC_IAR) Register
The
register maps each peripheral interrupt ID to a correspond-
SIC_IAR
ing IVG priority level. This is accomplished with 4-bit groupings that
translate to IVG levels as shown in
words,
Table 4-2
in order to configure a peripheral interrupt ID for a particular IVG prior-
ity. Refer to
Table 4-1 on page 4-3
mappings for this specific processor.
System Interrupt Assignment Register (SIC_IAR)
31 30 29 28 27 26
0
ID Grouping 7
ID Grouping 6
15 14 13 12 11 10
0
ID Grouping 3
ID Grouping 2
Figure 4-2. System Interrupt Assignment Register
Table 4-2. IVG Select Definitions
General-Purpose Interrupt Value in SIC_IAR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
ADSP-BF50x Blackfin Processor Hardware Reference
defines the value to write in a 4-bit field within
25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
9
8
7
0
0
0
0
0
0
0
0
0
1
2
3
4
5
System Interrupts
Table 4-2
and
Figure
for information on SIC_IAR
0
0
0
0
0
0
0
ID Grouping 4
ID Grouping 5
6
5
4
3
2
1
0
0
0
0
0
0
0
0
ID Grouping 1
4-2. In other
SIC_IAR
ID Grouping 0
4-11
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