Timer Counter Register (Timer_Counter) - Analog Devices ADSP-BF506F Hardware Reference Manual

Timer Registers
Timer Configuration Register (TIMER_CONFIG)
15 14 13 12 11 10
ERR_TYP[1:0] (Error
Type) - RO
00 - No error
01 - Counter overflow error
10 - Period register programming error
11 - Pulse width register programming error
EMU_RUN (Emulation Behavior Select)
0 - Timer counter stops during emulation
1 - Timer counter runs during emulation
TOGGLE_HI (PWM_OUT PULSE_HI
Toggle Mode)
0 - The effective state of PULSE_HI
is the programmed state
1 - The effective state of PULSE_HI
alternates each period
CLK_SEL (Timer Clock Select)
0 - Use system clock SCLK for counter
1 - Use PWM_CLK to clock counter
OUT_DIS (Output Pad Disable)
0 - Enable TMR pad in PWM_OUT mode
1 - Disable pad in PWM_OUT mode
Figure 10-19. Timer Configuration Register

Timer Counter Register (TIMER_COUNTER)

This read-only register retains its state when disabled. When enabled, the
TIMER_COUNTER
and mode. The
read at any time (whether the timer is running or stopped), and it returns
an atomic 32-bit value. Depending on the operating mode, the increment-
ing counter can be clocked by four different sources:
alternative timer clock pin
most likely used as the PPI clock (
10-42
9 8
0 0 0 0 0 0 0 0
register is reinitialized by hardware based on configuration
register, shown in
TIMER_COUNTER
TACLK
ADSP-BF50x Blackfin Processor Hardware Reference
7 6 5 4 3 2 1
0 0 0 0 0 0 0
Figure
, or the common
TMRCLK
).
PPI_CLK
0
0 Reset = 0x0000
TMODE[1:0] (Timer Mode)
00 - Reset state - unused
01 - PWM_OUT mode
10 - WDTH_CAP mode
11 - EXT_CLK mode
PULSE_HI
0 - Negative action pulse
1 - Positive action pulse
PERIOD_CNT (Period
Count)
0 - Count to end of width
1 - Count to end of period
IRQ_ENA (Interrupt
Request Enable)
0 - Interrupt request disable
1 - Interrupt request enable
TIN_SEL (Timer Input
Select)
PWM_OUT Mode
0 - Clock from TACLK
input if CLK_SEL = 1
1 - Clock from TMRCLK
input if CLK_SEL = 1
WDTH_CAP Mode
0 - Sample TMR pin input
1 - Sample TACI input
10-20, may be
, the pin, the
SCLK TMR
pin, which is