Functional Description; Rsi Clock Configuration - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description

The following sections describe the functions and features of the RSI
controller as well as the MMC, SD, SDIO, and CE-ATA protocols.
For detailed information on timing parameters and protocol
requirements, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F
Embedded Processor Data Sheet and the following standards and
specifications:
• MMCA System Specification
• JESD84 series of JEDEC standards
• SD Specifications Part 1 Physical Layer Specification
• SD Specifications Part 1 Physical Layer Simplified Specification
• SD Specifications Part E1 SDIO Specification

RSI Clock Configuration

The RSI is a fast, synchronous peripheral with a programmable clock fre-
quency that is supplied via the
RSI and the PAB/DAB busses operates at
tion between the clock domain that is supplied externally from the RSI on
the signal and the internal RSI access to the PAB and DAB busses
RSI_CLK
is accomplished using synchronizers in the RSI module. The
quency is configured via the 8-bit
of the
RSI_CLK_CONTROL
(RSI_CLK_CONTROL)" on page
If
CLKDIV_BYPASS
is derived directly from
If
CLKDIV_BYPASS
frequency, where
ADSP-BF50x Blackfin Processor Hardware Reference
RSI_CLK
CLKDIV
register (see
21-55).
is set, the clock frequency driven on the
.
SCLK
is cleared, the clock divider logic provides an
is an 8-bit value ranging between 0 and 255.
CLKDIV
Removable Storage Interface
signal. The interface between the
frequency. Communica-
SCLK
field and the
"RSI Clock Control Register
fre-
RSI_CLK
bit
CLKDIV_BYPASS
signal
RSI_CLK
RSI_CLK
21-9