Internal Interface; Description Of Operation - Analog Devices ADSP-BF506F Hardware Reference Manual

Description of Operation

Clock and capture input pins are sampled every
of every low or high state must be at least one
mum allowed frequency of timer input signals is

Internal Interface

Timer registers are always accessed by the core through the 16-bit PAB
bus. Hardware ensures that all read and write operations from and to
32-bit timer registers are atomic.
Every timer has a dedicated interrupt request output that connects to the
system interrupt controller (SIC).
Description of Operation
The core of every timer is a 32-bit counter, that can be interrogated
through the read-only
operation, the counter is reset to either 0x0000 0000 or 0x0000 0001
when the timer is enabled. The counter always counts upward. Usually, it
is clocked by
SCLK
input or, alternatively, the common timer clock input
TACLK
counter mode, the counter is clocked by edges on the
significant edge is programmable.
32
After 2 -1 clocks, the counter overflows. This is reported by the over-
flow/error bit
TOVF_ERR
counter mode, the counter is reset by hardware when its content reaches
the values stored in the
ter is reset by leading edges on the
events cause the interrupt latch
set and issue a system interrupt request. The
are sticky and should be cleared by software using W1C (write-1-to-clear)
operations to clear the interrupt request. The global
10-4
TIMER_COUNTER
. In PWM mode it can be clocked by the alternate clock
in the
TIMER_STATUS
TIMER_PERIOD
TMR
TIMIL
ADSP-BF50x Blackfin Processor Hardware Reference
cycle. The duration
SCLK
. Therefore, the maxi-
SCLK
/ .
SCLK 2
register. Depending on the mode of
TMR
register. In PWM and
register. In capture mode, the coun-
or input pin. If enabled, these
TACI
in the
TIMER_STATUS
and
TOVF_ERR
TIMER_STATUS
. In
TMRCLK
input pin. The
register to be
latches
TIMIL
register