Block Erase Command - Analog Devices ADSP-BF506F Hardware Reference Manual

Command Interface to Internal Flash Memory

Block Erase Command

The block erase command erases a block. It sets all the bits within the
selected block to '1'. All previous data in the block is lost. If the block is
protected then the erase operation aborts, the data in the block does not
change, and the status register outputs the error. The block erase com-
mand can be issued at any moment, regardless of whether the block has
been programmed or not.
Two bus write cycles are required to issue the command:
• The first bus cycle sets up the erase command
• The second latches the block address in the program/erase control-
ler and starts it
If the second bus cycle is not write erase confirm (0xD0), status register
bits and
SR4 SR5
asserted ( driven low). As data integrity cannot be guaranteed when the
RP
erase operation is aborted, the block must be erased again.
Once the command is issued, the device outputs the status register data
when any address within the bank is read. At the end of the operation the
bank remains in read status register mode until a read array, read CFI
query, or read electronic signature command is issued.
During erase operations the bank containing the block being erased only
accepts the read array, read status register, read electronic signature, read
CFI query and the program/erase suspend commands; all other commands
are ignored. Refer to
on page 6-36 for detailed information about simultaneous operations
allowed in banks not being erased. Typical erase times are given in the
ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data
Sheet.
See Figure 6-7 on page 6-60
flowchart and pseudo code for using the block erase command.
6-10
are set and the command aborts. Erase aborts if reset is
"Dual Operations and Multiple Bank Architecture"
and Listing 6-3 on page 6-61
ADSP-BF50x Blackfin Processor Hardware Reference
for a suggested