Analog Devices ADSP-BF506F Hardware Reference Manual page 345

DF
f
CLKIN
÷1 OR ÷2
Figure 8-1. PLL Block Diagram
Figure 8-1 illustrates a conceptual model of the PLL circuitry, configura-
tion inputs, and resulting outputs. In the figure, the VCO is an
ADSP-BF50x Blackfin Processor Hardware Reference
SCLK
f
CLKIN
LOOP
+
VCO
-
FILTER
×1,..., ×64
PHASE LOCKED LOOP
MSEL [5:0]
PLL_OFF DISABLE
CONTROL INPUT TO PLL.
CAN ADDITIONALLY BE
USED WITH BYPASS
CLKBUF
EN
EN
SELECT
EXTCLK CLKIN
C1 *
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. SEE PRODUCT DATA SHEET.
Dynamic Power Management
SSEL [3:0}
f
VCO
GATE
÷1,..., ÷15
÷1, ÷2, ÷4,
OR ÷8
OUTPUT CLOCK
GENERATOR (CLOCK
DIVIDE AND MUX)
CSEL [1:0]
BYPASS
(ACTIVE
MODE)
CCLK = SCLK = CLKIN
CLKOUT (SCLK)
TO PLL CIRCUITRY
560
XTAL
R1 *
FOR OVERTONE
OPERATION ONLY:
C2 *
SCLK
PDWN
DEEP SLEEP
POWERDOWN
(CCLK AND
SCLK OFF)
GATE
CCLK
STOPCK
(SLEEP MODE)
STOP CLOCK
CCLK OFF
8-3