Illegal States - Analog Devices ADSP-BF506F Hardware Reference Manual

without interrupt generation, set
at the system level. If enabled by
erated by error conditions as reported by the
The system interrupt controller enables flexible interrupt handling. All
timers may or may not share the same CEC interrupt channel, so that a
single interrupt routine services more than one timer. In PWM mode,
multiple timers may run with the same period settings and issue their
interrupt requests simultaneously. In this case, the service routine might
clear all
TIMIL
TIMER_STATUS
If interrupts are enabled, make sure that the interrupt service routine
(ISR) clears the
instruction executes. This ensures that the interrupt is not reissued.
Remember that writes to system registers are delayed. If only a few
instructions separate the
an extra
SSYNC
bit in the
TIMIL
rupt service routine to avoid missing any timer events.

Illegal States

Every timer features an error detection circuit. It handles overflow situa-
tions but also performs pulse width vs. period plausibility checks. Errors
are reported by the
bit field in the individual
ERR_TYP
vides a summary of error conditions, using these terms:
• Startup. The first clock period during which the timer counter is
running after the timer is enabled by writing
• Rollover. The time when the current count matches the value in
TIMER_PERIOD
ADSP-BF50x Blackfin Processor Hardware Reference
latch bits at once by writing 0x000F 000F to the
register.
bit in the
TIMIL TIMER_STATUS
clear command from the RTI instruction,
TIMIL
instruction may be inserted. In
register at the very beginning of the inter-
TIMER_STATUS
bits in the
TOVF_ERR
and the counter is reloaded with the value "1".
General-Purpose Timers
but leave the interrupt masked
IRQ_ENA
, interrupt requests are also gen-
IRQ_ENA
TOVF_ERR
register before the RTI
EXT_CLK
TIMER_STATUS
registers.
TIMER_CONFIG
bits.
mode, reset the
register and the
Table 10-1 pro-
.
TIMER_ENABLE
10-7