Spi Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

SPI Registers

SPI Registers
The SPI peripheral includes a number of user-accessible registers. Some of
these registers are also accessible through the DMA bus. Four registers
contain control and status information:
. Two registers are used for buffering receive and transmit data:
SPI_STAT
and
SPI_RDBR SPI_TDBR
module and is not directly accessible.
Table 18-3 shows the functions of the SPI registers.
Figure 18-18 provide details.
Table 18-3. SPI Register Mapping
Register Name Function
SPI_BAUD SPI port
baud control
SPI_CTL SPI port
control
SPI_FLG SPI port
flag
SPI_STAT SPI port
status
SPI_TDBR SPI port
transmit data buffer
SPI_RDBR SPI port
receive data buffer
SPI_SHADOW SPI port
data
18-34
. The shift register,
Notes
Value of "0" or "1" disables the serial clock
SPE and MSTR bits can also be modified by hardware
(when MODF is set)
Bits 0 and 8 are reserved
SPIF bit can be set by clearing SPE in SPI_CTL
Register contents can also be modified by hardware (by
DMA and/or when SZ = 1 in SPI_CTL)
When register is read, hardware events can be triggered
Register has the same contents as SPI_RDBR, but no
action is taken when it is read
ADSP-BF50x Blackfin Processor Hardware Reference
,
SPI_BAUD SPI_CTL
, is internal to the SPI
SFDR
Figure 18-12
, , and
SPI_FLG
through