Analog Devices ADSP-BF506F Hardware Reference Manual page 827

finished after it sends the last data and simultaneously receives the last
data bit. A transfer for a slave device ends after the last sampling edge of
.
SCK
The bit defines when the receive buffer can be read. The
RXS
defines when the transmit buffer can be filled. The end of a single word
transfer occurs when the
been received and latched into the receive buffer,
SPI, is set shortly after the last sampling edge of
RXS
is set shortly after the last
RXS
latency is typically a few
baud rate. If configured to generate an interrupt when
( = ), the interrupt goes active one
TIMOD b#00
When not relying on this interrupt, the end of a transfer can be detected
by polling the
To maintain software compatibility with other SPI devices, the
also available for polling. This bit may have a slightly different behavior
from that of other commercially available devices. For a slave device,
is cleared shortly after the start of a transfer (
first active edge of
a master device,
by writing the
and is set one-half
.
CPOL
The time at which
set after , but at the lowest baud rate settings (
RXS
bit is set before
, because of the latency. Therefore, for
SPI_RDBR
= 3,
SPI_BAUD
settings,
SPI_BAUD
If the SPI port is used to transmit and receive at the same time, or to
switch between receive and transmit operation frequently, then the
= mode may be the best operation option. In this mode,
TIMOD b#00
ADSP-BF50x Blackfin Processor Hardware Reference
bit is set, indicating that a new word has just
RXS
SCK
cycles and is independent of
SCLK
bit.
RXS
on = 1), and is set at the same time as
SCK CPHA
is cleared shortly after the start of a transfer (either
SPIF
or reading the
SPI_TDBR
period after the last
SCK
is set depends on the baud rate. In general,
SPIF
is set, and consequently before new data is latched into
RXS
must be set before
RXS
is guaranteed to be set before
RXS
SPI-Compatible Port Controller
SPI_RDBR
edge, regardless of
cycle after
SCLK
going low for
SPISS
, depending on
SPI_RDBR
edge, regardless of
SCK
SPI_BAUD
SPI_BAUD
to read
SPIF SPI_RDBR
bit
TXS
. For a master
. For a slave SPI,
SCK
or . The
CPHA CPOL
and the
TIMOD
is full
SPI_RDBR
is set.
RXS
bit is
SPIF
SPIF
= 0,
CPHA
. For
RXS
),
TIMOD
CPHA
SPIF
< 4). The
SPIF
= 2 or
. For larger
is set.
SPIF
18-23
or
is