Analog Devices ADSP-BF506F Hardware Reference Manual page 275

The
HMDMAx_ECINIT
the handshake mode is enabled (when the
0 to 1). If the initial edge count value is 0, the handshake operation starts
with a settled request budget. If positive, the engine starts immediately
transferring the programmed number (up to 32767) of blocks once
enabled, even without detecting any activity on the
tive, the engine will disregard the programmed number (up to 32768)
significant edges on the
Figure 7-3 illustrates how an asynchronous FIFO could be connected. In
such a scenario the
listen to falling edges. The Blackfin processor does not evaluate the full
flag such FIFOs usually provide because asynchronous polling of that sig-
nal would reduce the system throughput drastically. Moreover, the
processor first fills the FIFO by initializing the
1024, which equals the depth of the FIFO. Once enabled, the MDMA
automatically transmits 1024 data words. Afterward it continues to trans-
mit only if the FIFO is emptied by its read strobe again. Most likely, the
HMDMAx_BCINIT
BLACKFIN
D0 .. D15
AMSx
AWE
DMARx
Figure 7-3. Transmit DMA Example Connection
In the receive example shown in
does not use the FIFO's internal control mechanism. Rather than testing
the empty flag, the processor counts the number of data words available in
the FIFO in its own
could immediately process data as soon as it is written into the FIFO by
ADSP-BF50x Blackfin Processor Hardware Reference
registers reload the
inputs before starting normal operation.
DMARx
bit should be cleared to let the
REP
register is programmed to 1 in this case.
I0 .. I15
FF
WR
Figure
HMDMAx_ECOUNT
Direct Memory Access
HMDMAx_ECOUNT
bit changes from
HMDMAEN
DMARx
HMDMAx_ECINIT
1024K x 16 FIFO
O0 .. O15
RD
7-4, the Blackfin processor again
register. Theoretically, the MDMA
registers every time
pins. If nega-
request pin
DMARx
register to
7-39