Analog Devices ADSP-BF506F Hardware Reference Manual page 832

Programming Model
4. If configured for receive, once the slave select input is active, the
slave starts receiving and transmitting data on
in the shift register is loaded into the
of the transfer. As the SPI reads data from the
and writes to the SPI DMA FIFO, it requests a DMA write to
memory. Upon a DMA grant, the DMA engine reads a word from
the SPI DMA FIFO and writes to memory.
If configured for transmit, the SPI requests a DMA read from
memory. Upon a DMA grant, the DMA engine reads a word from
memory and writes to the SPI DMA FIFO. The SPI then reads
data from the SPI DMA FIFO and writes to the
awaiting the start of the next transfer. Once the slave select input is
active, the slave starts receiving and transmitting data on
The value in the
the start of the transfer.
5. In receive mode, as long as there is data in the SPI DMA FIFO
(FIFO not empty), the SPI slave continues to request a DMA write
to memory. The DMA engine continues to read a word from the
SPI DMA FIFO and writes to memory until the SPI DMA word
count register transitions from "1" to "0". The SPI slave continues
receiving words on
active.
In transmit mode, as long as there is room in the SPI DMA FIFO
(FIFO not full), the SPI slave continues to request a DMA read
from memory. The DMA engine continues to read a word from
memory and write to the SPI DMA FIFO until the SPI DMA word
count register transitions from "1" to "0". The SPI slave continues
transmitting words on
active.
See Figure 18-9 on page 18-31
18-28
register is loaded into the shift register at
SPI_TDBR
edges as long as the slave select input is
SCK
edges as long as the slave select input is
SCK
for additional information.
ADSP-BF50x Blackfin Processor Hardware Reference
edges. The value
SCK
register at the end
SPI_RDBR
SPI_RDBR
SPI_TDBR
register
register,
edges.
SCK