Rsi Fifo Counter Register (Rsi_Fifo_Cnt) - Analog Devices ADSP-BF506F Hardware Reference Manual

Table 21-22. RSI_MASKx Registers (Cont'd)
Bit Name
14 TX_FIFO_STAT_MASK
15 RX_FIFO_STAT_MASK
16 TX_FIFO_FULL_MASK
17 RX_FIFO_FULL_MASK
18 TX_FIFO_ZER/W_MASK
19 RX_DAT_ZER/W_MASK
20 TX_DAT_RDY_MASK
21 RX_FIFO_RDY_MASK
31:22 Reserved

RSI FIFO Counter Register (RSI_FIFO_CNT)

The
RSI_FIFO_CNT
32-bit words still to be read from or written to the FIFO.
loaded from the
RSI_DATA_CONTROL
(multiple of 4), the remaining 1 to 3 bytes are regarded as a word.
ADSP-BF50x Blackfin Processor Hardware Reference
register contains a value indicating the number of
register when the
RSI_DATA_LGTH
register is set. If the data length is not word-aligned
Removable Storage Interface
Function
Transmit FIFO watermark
0 = Disable interrupt
1 = Enable interrupt
Receive FIFO watermark
0 = Disable interrupt
1 = Enable interrupt
Transmit FIFO full
0 = Disable interrupt
1 = Enable interrupt
Receive FIFO full
0 = Disable interrupt
1 = Enable interrupt
Transmit FIFO empty
0 = Disable interrupt
1 = Enable interrupt
Receive FIFO empty
0 = Disable interrupt
1 = Enable interrupt
Transmit data available
0 = Disable interrupt
1 = Enable interrupt
Receive data available
0 = Disable interrupt
1 = Enable interrupt
Reserved
DATA_EN
Type Default
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
is
RSI_FIFO_CNT
bit of the
21-73