Twi Interrupt Mask Register (Twi_Int_Mask) - Analog Devices ADSP-BF506F Hardware Reference Manual

Register Descriptions

TWI Interrupt Mask Register (TWI_INT_MASK)

The
TWI_INT_MASK
output. Each mask bit corresponds with one interrupt source bit in the
TWI_INT_STAT
does not affect the contents of the
TWI Interrupt Mask Register (TWI_INT_MASK)
For all bits, 0 = Interrupt generation disabled, 1 = Interrupt generation enabled.
15 14 13 12 11 10
0
RCVSERVM (Receive FIFO
Service Interrupt Mask)
XMTSERVM (Transmit FIFO
Service Interrupt Mask)
MERRM (Master Transfer Error
Interrupt Mask)
MCOMPM (Master Transfer
Complete Interrupt Mask)
Figure 16-24. TWI Interrupt Mask Register
16-42
register enables interrupt sources to assert the interrupt
register. Reading and writing the
9 8
0 0 0 0 0 0 0
ADSP-BF50x Blackfin Processor Hardware Reference
TWI_INT_MASK
register.
TWI_INT_STAT
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
register
Reset = 0x0000
SINITM (Slave Transfer
Initiated Interrupt Mask)
SCOMPM (Slave Transfer
Complete Interrupt Mask)
SERRM (Slave Transfer Error
Interrupt Mask)
SOVFM (Slave Overflow
Interrupt Mask)