Rsi Power Control Register (Rsi_Pwr_Control) - Analog Devices ADSP-BF506F Hardware Reference Manual

RSI Registers
Table 21-11. RSI Module Registers (Cont'd)
Register Name
RSI_RD_WAIT_EN
RSI_PID0
RSI_PID1
RSI_PID2
RSI_PID3

RSI Power Control Register (RSI_PWR_CONTROL)

The
RSI_PWR_CONTROL
RSI module as well as the open-drain configuration for the
The field must be set to "11" in order for the RSI to be enabled.
PWR_ON
The
RSI_CMD_OD
nal in open-drain mode. The default mode of operation is push-pull. After
a data write, data cannot be written to this register for a five
RSI Power Control Register (RSI_PWR_CONTROL)
Read/Write
15 14 13 12 11 10
0xFFC0 3800
0
Reserved
Figure 21-6. RSI Power Control Register
21-54
Function
RSI read wait enable register
on page 21-80
RSI peripheral identifica-
tion registers
on page 21-81
register contains bits that control the power to the
bit, when set, results in the RSI driving the
9 8 7
0 0 0 0 0 0 0 0
ADSP-BF50x Blackfin Processor Hardware Reference
Address
0xFFC038CC R/W1A/W 16-bit
0xFFC038D0
0xFFC038D4
0xFFC038D8
0xFFC038DC
6 5 4 3 2 1 0
0 0 0 0 0 0 0
Type Access
R 16-bit
signal.
RSI_CMD
sig-
RSI_CMD
cycles.
SCLK
Reset = 0x0000
PWR_ON
Reserved
RSI_CMD_OD