Processor-Specific Mmrs; Dmem_Control Register - Analog Devices ADSP-BF506F Hardware Reference Manual

Processor-Specific MMRs

The complete set of memory-related MMRs is described in the Blackfin
Processor Programming Reference. Several MMRs have bit definitions spe-
cific to the processors described in this manual. These registers are
described in the following sections.

DMEM_CONTROL Register

The data memory control register (
contains control bits for the L1 data memory.
Data Memory Control Register (DMEM_CONTROL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0xFFE0 0004
0
15 14 13 12 11 10
0
DCBS (L1 Data Cache Bank Select)
Valid only when DMC = 1. Determines whether
Address bit A[14] or A[23] is used to select the L1
data cache bank.
0 - Address bit 14 is used to select Bank A
for cache access. If bit 14 of address is 1,
select L1 Data Memory Data Bank A; if bit 14
of address is 0, no bank selected.
1 - Address bit 23 is used to select Bank A for
cache access. If bit 23 of address is 1, select
L1 Data Memory Data Bank A; if bit 23 of
address is 0, no bank selected.
Figure 2-2. L1 Data Memory Control Register

Note that both DAG 0 and 1 use Port-A for non-cacheable fetches.
ADSP-BF50x Blackfin Processor Hardware Reference
0 0 0 0 0 0 0 0
9 8 7
0 0 0 0 0 0 0 0
), shown in
DMEM_CONTROL
0 0 0 0 0 0 0
6 5 4 3 2 1 0
0 0 0 0 0 0 1
Memory
Figure 2-2,
Reset = 0x0000 1001
ENDCPLB (Data Cacheability
Protection Lookaside Buffer
Enable)
0 - CPLBs disabled. Minimal
address checking only
1 - CPLBs enabled
DMC (L1 Data Memory
Configure)
For ADSP-BF50x:
0 - Data Bank A is SRAM,
also invalidates all
cache lines if previously
configured as cache
1 - Data Bank A is lower
16K byte SRAM, upper
16K byte cache
2-5