Functional Description
acknowledged, the application software is responsible for correct interpre-
tation of the events. It is recommended to logically
and
CNT_IMASK
rupt requests are cleared by write-one-to-clear (W1C) operations to the
register. Hardware does not clear the status bits automatically,
CNT_STATUS
unless the counter module is disabled.
Illegal Gray/Binary Code Events
When the illegal transitions described in
page 13-4
or
"Binary Encoder Mode" on page 13-5
the
CNT_STATUS
register, an interrupt request is generated. The
in the quadrature encoder or binary encoder modes.
Up/Down Count Events
The
bit in the
UCII
been incremented. Similarly, the
events are independent. For instance, if the counter first increments by
one and then decrements by two, both bits remain set, even though the
resulting counter value shows a decrement by one. In up/down counter
mode, hardware may detect simultaneous active edges on the
inputs. In that case, the
and
UCII
DCII
Interrupt requests for these events may be enabled through the
bits. This feature should be used carefully when the counter is
DCIE
clocked at high rates. This is especially critical when the counter operates
in
mode, as interrupts would be generated every
DIR_TMR
These events can also be used for additional push buttons, if GP counter
features are not needed. When up/down counter mode is enabled, these
count events can be used to report interrupts from push buttons that con-
nect to the
CUD
13-12
registers to identify pending interrupts. Inter-
CNT_STATUS
register is set. If enabled by the
register indicates whether the counter has
CNT_STATUS
CNT_COUNTER
bits are set.
and
inputs.
CDG
ADSP-BF50x Blackfin Processor Hardware Reference
"Quadrature Encoder Mode" on
ICIE
ICIE
bit reports decrements. The two
DCII
remains unchanged, but both the
the content of the
AND
occur, the
bit in
ICII
bit in the
CNT_IMASK
bit should only be set
and
CUD
and
UCIE
cycle.
SCLK
CDG
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