Powering Down The Core (Hibernate State) - Analog Devices ADSP-BF506F Hardware Reference Manual

Dynamic Power Management Controller
value. That in turn will set the
end of your "wait" state for the voltage regulator to settle.

Powering Down the Core (Hibernate State)

The external regulator can be signaled to shut off V
signal. Writing 0 to the
EXT_WAKE
which disables
will transition high if any wakeup sources occur, which will signal the
external voltage regulator to turn V
are several user-selectable events, all of which are controlled in the
register:
• Assertion of the
no modification to
• External GPIO event. Set a GPIO wakeup enable control bit
( ,
PH0WE
the corresponding pin.
• External CAN RX event. Set the CAN RX wakeup enable control
( ) bit to enable wakeup on the occurrence of a CAN RX
CANWE
event.
• Pin
EXT_WAKE
EXT_WAKE
wakeup sources, except hardware reset. The pin follows the wakeup
signal of the various wakeup sources.

When the core is powered down, V
internal state of the processor is not maintained, with the exception
of the
VR_CTL
internally (memory contents, register contents, and so on) must be
written to a non-volatile storage device prior to removing power.
8-18
VSAT
and , will also make
CCLK SCLK
pin always exits hibernate state and requires
RESET
VR_CTL
, ) to enable wakeup on assertion of a signal on
PF8WE PF9WE
is provided to indicate the occurrence of wakeup.
is an output pin, which is a logical OR of the above
register. Therefore, any critical information stored
ADSP-BF50x Blackfin Processor Hardware Reference
bit, which should be considered the
bit of the
HIBERNATEB
EXT_WAKE
on again. The wakeup sources
DDINT
.
is set to 0 V, and the
DDINT
using the
DDINT
register,
VR_CTL
go low.
EXT_WAKE
VR_CTL