Support For H.100 Standard Protocol; 2× Clock Recovery Control - Analog Devices ADSP-BF506F Hardware Reference Manual

transmitted or received would be placed at addresses 1 and 10 of the buf-
fer, and the rest of the words in the DMA buffer would be ignored. This
mode allows changing the number of enabled channels while the SPORT
is enabled, with some caution. First read the channel register to make sure
that the active window is not being serviced. If the channel count is 0,
then the multichannel select registers can be updated.

Support for H.100 Standard Protocol

The processor supports the H.100 standard protocol. The following
SPORT parameters must be set to support this standard.
• Set for external frame sync. Frame sync generated by external bus
master.
•
TFSR/RFSR
•
LTFS/LRFS
• Set for external clock
• set (multichannel mode selected)
MCMEN
• = 0 (no frame delay between frame sync and first data bit)
MFD
• = 7 (8-bit words)
SLEN
• = 1 (set for H.100 configuration, enabling half-clock-cycle
FSDR
early frame sync)
2× Clock Recovery Control
The SPORT can recover the data rate clock from a provided 2× input
clock. This enables the implementation of H.100 compatibility modes for
MVIP-90 (2 Mbps data) and HMVIP (8 Mbps data), by recovering
2 MHz from 4 MHz or 8 MHz from the 16 MHz incoming clock with
the proper phase relationship. A 2-bit mode signal (
ADSP-BF50x Blackfin Processor Hardware Reference
set (frame syncs required)
set (active low frame syncs)
SPORT Controller
in the
MCCRM[1:0]
19-25