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Description of Operation
Figure 18-6
shows the SPI transfer protocol for
toggling in the middle of the data transfer,
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
SPISS
(TO SLAVE)
Figure 18-6. SPI Transfer Protocol for CPHA = 0
Figure 18-7
shows the SPI transfer protocol for
toggling at the beginning of the data transfer,
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
SPISS
(TO SLAVE)
Figure 18-7. SPI Transfer Protocol for CPHA = 1
18-14
1
2
3
*
MSB
6
5
MSB
6
5
(* = UNDEFINED)
1
2
3
*
MSB
6
5
MSB
6
5
*
(* = UNDEFINED)
ADSP-BF50x Blackfin Processor Hardware Reference
= 0. Note
CPHA
= 0, and
SIZE
4
5
6
7
4
3
2
1
4
3
2
1
= 1. Note
CPHA
= 0, and
SIZE
4
5
6
7
4
3
2
1
4
3
2
1
starts
SCK
= 0.
LSBF
8
LSB
*
LSB
*
starts
SCK
= 0.
LSBF
8
LSB
*
LSB
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