Pwm Dead Time (Pwm_Dt) Register; Pwm Chopping Control (Pwm_Gate) Register - Analog Devices ADSP-BF506F Hardware Reference Manual

PWM Registers

PWM Dead Time (PWM_DT) Register

The register controls the dead time interval of the generated PWM
PWM_DT
patterns. Bit diagrams and descriptions are provided in
Table 14-7.
PWM Dead Time Register (PWM_DT)
15 14 13 12 11 10
0 0
Reserved
Figure 14-13. PWM Dead Time Register
Table 14-7. PWM_DT Register
Bit Name
9:0 PWM_DT
15:10 Reserved

PWM Chopping Control (PWM_GATE) Register

The PWM controller permits the mixing of the output PWM signals with
a high-frequency chopping signal. The features of gate-drive-chopping
mode are controlled
by the
PWM_GATE
Figure 14-14 and
14-42
9 8 7 6
0 0 0 0 0 0 0 0
register. Bit diagrams and descriptions are provided in
Table 14-8.
ADSP-BF50x Blackfin Processor Hardware Reference
5 4 3 2 1 0
0 0 0 0 0 0
PWM_DT
Function
PWM dead time (unsigned)
Figure 14-13 and
Reset = 0x0000
Type Default
RW 0
0