Event Register Pairs; Event Comparators; Timing Generation Unit - Analog Devices ADSP-BF506F Hardware Reference Manual


A latency of no more than 4 SCLK cycles exists between external
trigger and ACMTMRx count start. Refer to
Latency" on page 22-18

Event Register Pairs

The ACM has 16 event register pairs. Each pair consists of an
register and an
lar event and determines the ADC control settings for the particular event.
The register determines when the ADC sampling happens corre-
ACM_ETx
sponding to the event. Assignment of the 16 event register pairs: either 8
can be assigned to each of the timers (if both timers are enabled) or all 16
can be assigned to one particular timer (if only one timer is enabled).

Event Comparators

There are 16 event time comparators to determine when an enabled event
should happen. The comparators compare the event time with the corre-
sponding timer count. If the time value matches, the comparators signal
an active event signal to the timing generation unit. If more than one
event is active during the same SCLK cycle, only the highest priority event
is processed, and all other events are missed (even if there was space in the
pending event FIFO). The priority of events is fixed, with event 0 having
highest priority and event 15 having lowest priority.

Timing Generation Unit

The timing generation unit generates the ADC control signals based on
the register setting. The timings of external signals (
ACM_ERx
[2:0], , and others) are determined by the
A RANGE
event happens when another event is ongoing, the occurred event is stored
in the pending event FIFO. After the current event completes, the pend-
ing event is serviced (for example, the ACM starts an ADC conversion for
the event that occurred). If an event occurs when the pending event FIFO
ADSP-BF50x Blackfin Processor Hardware Reference
for further details.
register. The
ACM_ETx
ADC Control Module (ACM)
"ADC Sampling
register enables the particu-
ACM_ERx
ACM_TCx
ACM_ERx
, ,
ACLK CS
registers. If an
22-9