Peripherals; Memory Architecture - Analog Devices ADSP-BF506F Hardware Reference Manual

Peripherals

Peripherals
The ADSP-BF50x processors contain a rich set of peripherals connected
to the core via several high-bandwidth buses, providing flexibility in sys-
tem configuration as well as excellent overall system performance. (See
Figure 1-1.) Most of the peripherals are supported by a flexible DMA
structure. There are also two separate memory DMA channels dedicated
to data transfers between the processor's memory spaces. Multiple on-chip
buses provide enough bandwidth to keep the processor core running even
when there is also activity on all of the on-chip and external peripherals.
VOLTAGE REGULATOR INTERFACE
B
L1 INSTRUCTION
MEMORY
EAB 16
32M BIT
FLASH
Figure 1-1. ADSP-BF50x Processor Block Diagram

Memory Architecture

The Blackfin processor architecture structures memory as a single, unified
4G byte address space using 32-bit addresses. All resources, including
internal memory, external memory, and I/O control registers, occupy sep-
arate sections of this common address space. The memory portions of this
1-4
WATCHDOG TIMER
JTAG TEST AND EMULATION
INTERRUPT
CONTROLLER
L1 DATA
DMA
MEMORY
CONTROLLER
DCB
DEB
MEMORY PORT
FLASH CONTROL
ADSP-BF50x Blackfin Processor Hardware Reference
COUNTER1–0
PERIPHERAL
ACCESS BUS
DMA
ACCESS
BUS
BOOT
ROM
TIMER7–0
PWM 1–0
SPORT1–0
SPI1–0
UART1–0
PPI
RSI
ACM
CAN
TWI
GPIO
PORT F
PORT G
PORT H
ADC