Internal Memory; External Memory - Analog Devices ADSP-BF506F Hardware Reference Manual

Memory Architecture

Internal Memory

The processor has three blocks of on-chip memory that provide high
bandwidth access to the core:
• L1 instruction memory, consisting of SRAM and a 4-way set-asso-
ciative cache. This memory is accessed at full processor speed.
• L1 data memory, consisting of SRAM and/or a 2-way set-associa-
tive cache. This memory block is accessed at full processor speed.
• L1 scratchpad RAM, which runs at the same speed as the L1 mem-
ories but is only accessible as data SRAM and cannot be configured
as cache memory.

External Memory

External memory is accessed via the EBIU memory port. This 16-bit
interface provides a glue-less connection to the internal flash memory and
boot ROM. The EBIU on the processor interfaces with an internal flash
memory on the ADSP-BF504F and ADSP-BF506F devices. The internal
chip flash memory is a 32M bit (
features of this memory include:
• Synchronous/asynchronous read
• Synchronous burst read mode: 50 MHz
• Asynchronous/synchronous read mode
• Random access times: 70 ns
• Synchronous burst read suspend
• Memory blocks
• Multiple bank memory array: 4 Mbit banks
1-6
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16, multiple bank, burst) memory. The
ADSP-BF50x Blackfin Processor Hardware Reference