What's New In This Manual - Analog Devices ADSP-BF506F Hardware Reference Manual

• Chapter 24, "System Reset and Booting"
Describes the booting methods, booting process and specific boot
modes for the processor.
• Chapter 25, "System Design"
Describes how to use the processor as part of an overall system. It
includes information about bus timing and latency numbers, sema-
phores, and a discussion of the treatment of unused pins.
• Appendix A, "System MMR Assignments"
Lists the memory-mapped registers included in this manual, their
addresses, and cross-references to text.
• Appendix B, "Test Features"
Describes test features for the processor, discusses the JTAG stan-
dard, boundary-scan architecture, instruction and boundary
registers, and public instructions.

This hardware reference is a companion document to Blackfin Pro-
cessor Programming Reference.

What's New in This Manual

This is Revision 1.2 of ADSP-BF50x Blackfin Processor Hardware Refer-
ence. This revision corrects minor typographical errors and the following
issues:
• Core priority over DMA when accessing L1 SRAM in
"Chip Bus Hierarchy"
• Arithmetic operators in PLL block diagram, note on programming
the
STOPCK
ple in Chapter 8, "Dynamic Power Management"
• Assignment of
Ports"
ADSP-BF50x Blackfin Processor Hardware Reference
bit, and extra pipe in the
data registers in
GPIO
Chapter 3,
bfrom_SysControl
Chapter 9, "General-Purpose
Preface
code exam-
lv