Usage Notes; Module Stop Mode Setting; On-Chip Ram; Dtce Bit Setting - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

Hide thumbs Also See for H8S Series:

Table of Contents

Section 8 Data Transfer Controller (DTC)

Usage Notes

DTC operation can be disabled or enabled using the module stop control register. The initial

setting is for DTC operation to be halted. Register access is enabled by clearing module stop

mode. For details, refer to section 20, Power-Down Modes.

The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the

DTC is used, the RAME bit in SYSCR must not be cleared to 0.

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts

are masked, multiple activation sources can be set at one time (only at the initial setting) by

writing data after executing a dummy read on the relevant register.

Rev. 6.00 Mar 15, 2006 page 126 of 570

REJ09B0211-0600