Functional Block And Cpu (Dsp Core) Diagram - Texas Instruments TMS320C6712D User Manual

functional block and CPU (DSP core) diagram

SDRAM
SBSRAM 16
Interface
SRAM
ROM/FLASH
Timer 0
I/O Devices
Multichannel
Buffered
Serial Port 1
Framing Chips:
(McBSP1)
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
Multichannel
SPI Devices,
Buffered
Codecs
Serial Port 0
(McBSP0)
† In addition to fixed-point instructions, these functional units execute floating-point instructions.
‡ The device has a software-configurable PLL (with x4 through x25 multiplier and /1 through /32 divider) and a PLL Controller.
External
Memory
(EMIF)
Timer 1
Enhanced
DMA
Controller
(16 channel)
Interrupt
Selector
GPIO
POST OFFICE BOX 1443
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
Digital Signal Processor
Instruction Fetch
L2
Instruction Dispatch
Memory
4 Banks
Instruction Decode
64K Bytes
Data Path A
Total
A Register File
.L1 † .S1 † .M1 † .D1
Power-Down
Logic
PLL ‡
•
HOUSTON, TEXAS 77251−1443
TMS320C6712D
L1P Cache
Direct Mapped
4K Bytes Total
C67x CPU (DSP Core)
Control
Registers
Control
Logic
Data Path B
Test
B Register File
In-Circuit
Emulation
Interrupt
.D2 .M2 † .S2 † .L2 †
Control
L1D Cache
2-Way Set
Associative
4K Bytes Total
Boot
Configuration
9