Usb Endpoint Stall Register (Usbepstl) - Renesas HD6417641 Hardware Manual

Bit Bit Name
0 EP1DMAE

20.3.21 USB Endpoint Stall Register (USBEPSTL)

The bits in USBEPSTL are used to forcibly stall the endpoints on the application side. While a bit
is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for
endpoint 0 (EP0STL) is cleared automatically on reception of 8-bit command data for which
decoding is performed in this function module. When the SETUPTS flag in USBIFR0 is set,
writing 1 to the EP0STL bit is ignored. For details, see section 20.6, Stall Operations. When
ASCE = 1 is specified, the EPxSTL bit is automatically cleared.
USBEPSTL can be initialized to H'00 by a power-on reset.
Bit Bit Name

7 to 5
4 ASCE
3 EP3STL
Initial
Value R/W Description
0 R/W Endpoint 1 DMA Transfer Enable
When this bit is set, DMA transfer is enabled from the
endpoint 1 receive FIFO buffer to memory. If there is
at least one byte of receive data in the FIFO buffer, a
transfer request is asserted for the DMA controller. In
DMA transfer, when all the received data is read, EP1
is read automatically and the completion trigger
operates.
Also, as EP1-related interrupt requests to the CPU
are not automatically masked, interrupt requests
should be masked as necessary in the interrupt
enable register.
Initial
Value R/W Description
All 0 R Reserved
The write value should always be 0.
0 R/W Auto-Stall Clear Enable
When this bit is set to 1, the stall setting bit
(USBEPSTLR/ESxSTL) of the USB endpoint is
automatically cleared after a stall handshake is
returned to the host. This bit cannot be set for each
endpoint.
0 R/W EP3 Stall
When this bit is set to 1, endpoint 3 is placed in the
stall state.
Section 20 USB Function Module
Rev. 4.00 Sep. 14, 2005 Page 763 of 982
REJ09B0023-0400