Programming And Verification - Renesas F-ZTAT H8 Series Hardware Manual

Section 18 ROM
18.3.1

Programming and Verification

An efficient, high-speed programming procedure can be used to program and verify PROM data.
This procedure programs the chip quickly without subjecting it to voltage stress and without
sacrificing data reliability. Unused address areas contain H'FF data. Figure 18.4 shows the basic
high-speed programming flowchart. Tables 18.5 and 18.6 list the electrical characteristics of the
chip during programming. Figure 18.5 shows a timing chart.
No
Fail
Rev. 7.00 Sep 21, 2005 page 574 of 878
REJ09B0259-0700
Set programming/verification mode
V = 6.0 V ± 0.25 V, V
CC
Yes
<
n 25
Program with t
No
Verification OK?
Program with t
Set read mode
V = 5.0 V ± 0.25 V, V
CC
No
Figure 18.4 High-Speed Programming Flowchart
Start
= 12.5 V ± 0.3 V
PP
Address = 0
n = 0
→
n + 1 n
= 0.2 ms ± 5%
PW
Yes
= 0.2n ms
OPW
No
Last address?
Yes
= V
PP CC
All addresses
read?
Yes
End
→
Address + 1 address