Example Of Pcb Layout Image (17 Mm Square Bga Package); L1 And L2 (17 Mm Square Bga Package); L3 And L4 (17 Mm Square Bga Package); Figure 7.5 Example Of Pcb Layout Image (L1 And L2) (17 Mm Square Bga Package) - Renesas R-IN32M4-CL3 User Manual

R-IN32M4-CL3 User's Manual: Board design edition
7.6

Example of PCB Layout Image (17 mm Square BGA Package)

This section describes the peripheral circuit configuration of the 2.5-V built-in regulator installed in the R-IN32M4-CL3
in a 17 mm square BGA package.
7.6.1

L1 and L2 (17 mm Square BGA Package)

Followings are layout conditions and an example of PCB layout image (at the lower left of the L1 and L2).
 Separate AGND of the built-in regulator from Digital GND as far as possible.
 Do not pass through AGND under the MDI signal and the inductor component (L).
 Place C
as close to the power supply pins (VDDREG_33 and AVDDREG_33).
BYPASS
Also, place L, C , and C
IN
priority.
 Minimize the parasitic inductance of AVDDREG_33 pattern as small as possible.
Bypass capacitor
―can also place on L4―
for VDDREG_33
Connect to GND
Bypass capacitor for
AVDDREG_33
Connect to AGND
Place CBYPASS as close to the power supply pin (VDDREG_33 and AVDDREG_33).
Also, place C
Do not place CIN and COUT side by side to prevent noise propagation.

Figure 7.5 Example of PCB Layout Image (L1 and L2) (17 mm Square BGA Package)

7.6.2

L3 and L4 (17 mm Square BGA Package)

Followings are layout conditions and an example of PCB layout image (at the lower left of the L3 and L4).
PCB L3 (VDD)
AGND
L3 at this position, where L2 is AGND,
is preferably AGND than other power
sources.

Figure 7.6 Example of PCB Layout Image (L3 and L4) (17 mm Square BGA Package)

R18UZ0074EJ0100
Dec 24, 2019
as close to the relevant pins as possible. In particular, placement of C
OUT
PCB L1
REG_
EN
REG_
FB
AGND
P0_ P0_ P0_
REG_
AGND
OUT D3N D2N D1N D0N
P0_ P0_ P0_
VDD AVDD
REG_33 REG_33 D3P D2P D1P D0P
C C
BYPASS BYPASS
Use a GND guard around the
MDI signals.
C
IN
Minimize parasitic inductance
to AVDDREG_33.
as close to the relevant pin as possible. (Placement of C
IN
REG_
EN
REG_
FB
AGND
P0_ P0_ P0_ P0_
REG_
AGND
OUT D3N D2N D1N D0N
P0_ P0_ P0_ P0_
VDD AVDD
D3P D2P D1P D0P
REG_33 REG_33
Place SBD, L, and C compactly in front
OUT
of this to connect to the PCB.
Don't make an unnecessarily wide pattern
to avoid functioning as an antenna.
SBD: Schottky Barrier Diode
7. 2.5-V built-in Regulator Peripheral Circuit Configuration
PCB L2 (GND)
P0_
AGND
P0_
Connect to GND at a single-
point ground in front of this.
(In this case, do not use a
ferrite bead.)
is high priority than that of SBD, Inductor, and C
IN
PCB L4
REG_
EN
AGND
REG_OUT
P0_
REG_
AGND
OUT D3N
P0_
VDD AVDD
D3P
REG_33 REG_33
SBD
C
L
OUT
IN
REG_
EN
REG_
FB
AGND
P0_ P0_ P0_ P0_
REG_
AGND
OUT D3N D2N D1N D0N
P0_ P0_ P0_ P0_
VDD AVDD
REG_33 REG_33 D3P D2P D1P D0P
Do not pass AGND under the
MDI signal and the inductor
component (L).
.)
OUT
REG_
FB
REG_FB
P0_ P0_ P0_
D2N D1N D0N
P0_ P0_ P0_
D2P D1P D0P
This pattern is a 2.5-V feedback voltage after
smoothing with the inductor (L) and capacitor (C
Keep away from the regulator related signals and
the inductor (L).
is a high
).
OUT
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