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Section 31 Electrical Characteristics
31.3.5
Timing of On-Chip Peripheral Modules
Tables 31.10 to 31.13 show the on-chip peripheral module timing. The on-chip peripheral modules
that can be operated by the subclock (φSUB = 32.768 kHz) are I/O ports, external interrupts (NMI,
IRQ0 to IRQ15), watchdog timer, and 8-bit timer (channels 0 and 1) only.
Table 31.10 Timing of On-Chip Peripheral Modules
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ SUB = 32.768 kHz*, φ = 20 MHz to 34 MHz
Item
I/O ports Output data delay time
Input data setup time
Input data hold time
PWMX
Timer output delay time
SCI
Input clock cycle Asynchronous t
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
(synchronous)
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
A/D
Trigger input setup time
converter
RESO output delay time
WDT
RESO output pulse width
Note:
Only the peripheral modules that can be used in subclock operation.
*
Rev. 1.00 Mar. 12, 2008 Page 1146 of 1178
REJ09B0403-0100
Symbol
t
PWD
t
PRS
t
PRH
t
PWOD
Scyc
Synchronous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
t
RESD
t
RESOW
Min.
Max. Unit
29.4
ns
19.6
19.6
29.4
ns
4
t
cyc
6
0.4
0.6
t
Scyc
1.5
t
cyc
1.5
29.4
ns
19.6
19.6
19.6
ns
50
ns
132
t
cyc
Test Conditions
Figure 31.22
Figure 31.23
Figure 31.24
Figure 31.25
Figure 31.26
Figure 31.27
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