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Section 31 Electrical Characteristics
31.3.3
Bus Timing
Table 31.8 shows the bus timing. In subclock (φSUB = 32.768 kHz) operation, external expansion
mode operation cannot be guaranteed.
Table 31.8 Bus Timing
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item
Address delay time
Address setup time
Address hold time
CS delay time (IOS,
CS256)
AS delay time
HBE delay time
LBE delay time
RD delay time 1
RD delay time 2
Read data setup time
Read data hold time
Read data access time 1 t
Read data access time 2 t
Read data access time 3 t
Read data access time 4 t
Read data access time 5 t
WR delay time 1
WR delay time 2
WR pulse width 1
WR pulse width 2
Write data delay time
Write data setup time
Write data hold time
WAIT setup time
WAIT hold time
Rev. 1.00 Mar. 12, 2008 Page 1134 of 1178
REJ09B0403-0100
Symbol
Min.
t
AD
0.5 × t
t
–14.7
AS
cyc
0.5 × t
t
– 9.7
AH
cyc
t
CSD
t
ASD
t
HBD
t
LBD
t
RSD1
t
RSD2
t
14.7
RDS
t
0
RDH
ACC1
ACC2
ACC3
ACC4
ACC5
t
WRD1
t
WRD2
1.0 × t
– 19.6
t
WSW1
cyc
1.5 × t
– 19.6
t
WSW2
cyc
t
WDD
t
0
WDS
0.5 × t
t
– 5
WDH
cyc
t
24.7
WTS
t
5
WTH
Max.
Unit
14.7
ns
14.7
14.7
t
+ 5.0
AD
t
+ 5.0
AD
14.7
14.7
1.0 × t
– 29.4
cyc
1.5 × t
– 24.7
cyc
2.0 × t
– 29.4
cyc
2.5 × t
– 24.7
cyc
3.0 × t
– 29.4
cyc
14.7
14.7
24.7
Test Conditions
Figures 31.12 to
31.19
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