Motorola MPC860 PowerQUICC User Manual page 596

Part V. The Communications Processor Module
Note that if the receive and transmit clocks and the synchronization signals are common,
L1TSYNCx and L1TCLKx are not needed.
21.2.2 Enabling Connections to the TSA
Each SCC and SMC can be independently enabled to connect to the TSA. The SCCs are
connected to the TSA by programming the SI clock route register SICR[SCx]; see
Section 21.2.4.3, ÒSI Clock Route Register (SICR).Ó The SMCs are connected to the TSA
by setting the mode register SIMODE[SMCx]; see Section 21.2.4.2, ÒSI Mode Register
(SIMODE).Ó The general mode register SIGMR[ENx] must also be set to enable the
individual TDM channels; see Section 21.2.4.1, ÒSI Global Mode Register (SIGMR).Ó
Once the connections are made, the exact routing is determined in the SI RAM. See
Figure 21-4.
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
Figure 21-4. Enabling Connections through the SI
21.2.3 SI RAM
The 512-byte SI RAM contains the SCC and SMC routing information for the TDM
channels. The SI RAM totals 128 32-bit entriesÑ64 entries each for receive and transmit
routing. Representing one time slot, an entry controls from 1 to 16 bits/bytes and up to four
strobe pins (all active high).
21-8
Time-Slot
Assigner
SI RAM
Control Logic
SICR[SC1]=1
SICR[SC2]=1
SICR[SC3]=1
SICR[SC4]=1
SIMODE[SMC1]=1
SIMODE[SMC2]=1
MPC860 PowerQUICC UserÕs Manual
SIGMR[ENa]=1 to enable TDMa
TDMa Pins
ENa
ENb
TDMb Pins
SIGMR[ENb]=1 to enable TDMb
SICR[SC1]=0
SCC1 Pins
SICR[SC2]=0
SCC2 Pins
SICR[SC3]=0
SCC3 Pins
SICR[SC4]=0
SCC4 Pins
SIMODE[SMC1]=0
SMC1 Pins
SIMODE[SMC2]=0
SMC2 Pins
Multiplexed
Interface
Non-Multiplexed Interface
(clocking paths not shown)
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