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CLKOUT
GCLK1
A[0:31]
TS
R/W
D[0:31]
TA
CS1 (RAS)
BS[0:3] (CAS[0:3])
BDIP
SDACK1
DREQ0
Figure 20-15. Single-Address IDMA1 Burst Timing (Single-Buffer Mode)
20.3.10 External Recognition of an IDMA Transfer
The following are ways to externally determine if IDMA is executing a bus cycle:
¥ Monitor the AT signals of the SDMA channels for the user-deÞned function code.
(AT0 is always high for a DMA access.)
¥ Monitor SDACK, which shows accesses to the peripheral. SDACK activates on
either the source or destination bus cycles, depending on DCMR[S/D]. Note that if
Ethernet is running, this method does not work since SCCs in Ethernet mode also
toggle SDACK for SDMA transfers.
MOTOROLA
Row
Column 1
Column 2
Chapter 20. SDMA Channels and IDMA Emulation
Part V. The Communications Processor Module
Column 3
Column 4
20-21
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