Motorola MPC860 PowerQUICC User Manual page 575

Table 20-6. IDSR1/IDSR2 Field Descriptions (Continued)
Bits Name
6 DONE Buffer chain done. Indicates IDMA transfer termination. Set after servicing a BD that has its L bit
(last) set, regardless of the I bit setting.
7 OB Out of buffers. Indicates that the IDMA channel has no valid BDs left in the BD table.
20.3.3.3 IDMA Mask Registers (IDMR1 and IDMR2)
The read/write IDMA mask registers (IDMR1 and IDMR2) have the same format as IDSR,
shown in Figure 20-6. If an IDMR bit is set, the corresponding interrupt is enabled in
IDSRn; if it is cleared, the corresponding interrupt is masked. Reset clears IDMR.
IDMR1Õs internal address (IMMR offset) is 0x914; IDMR2Õs is 0x91C.
20.3.4 IDMA Buffer Descriptors (BD)
An IDMA buffer descriptor contains the speciÞc transfer information needed for its buffer.
IDMA BDs contain a status-and-control Þeld, the function code registers, the buffer length,
and the source and destination buffer pointers. The BDs are grouped together in contiguous
dual-port RAM to form a standard BD table; see Figure 20-7.
IDMAx BD Base
Address (IBASE)
Source Device or
Buffer 0
Source Device or
Buffer 1
Source Device or
Buffer 2
¥
¥ ¥
Source Device or
Buffer n
An IDMA descriptor breaks down as follows:
¥ The half word at (offset + 0) is the status-and-control Þeld.
¥ The byte at (offset + 2) is the destination function code register (DFCR). See
Section 20.3.4.1, ÒFunction Code RegistersÑSFCR and DFCR.Ó
MOTOROLA
BD 0
BD 1
BD 2
¥
¥
¥
BD n
Figure 20-7. IDMAx ChannelÕs BD Table
Chapter 20. SDMA Channels and IDMA Emulation
Part V. The Communications Processor Module
Description
Destination Device or
Buffer 0
Destination Device or
Buffer 1
Destination Device or
Buffer 2
Destination Device or
Buffer n
¥
¥ ¥
20-9