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11.5.3 SIU Interrupt Processing
Figure 11-8 shows the general ßow of SIU interrupt processing.
Assert External Interrupt
11.5.3.1 Nonmaskable InterruptsÑIRQ0 and SWT
Figure 11-9 is a logical representation of IRQ0.
SIEL[ED0]
IRQ0
Table 11-8 describes the differences between IRQ0 and other IRQ interrupts.
MOTOROLA
SIU Interrupt Occurs
Set Bit in SIPEND
Bit Set in SIMASK
to Core
Figure 11-8. SIU Interrupt Processing
MUX
Level
FF
Edge
Q
Q
R
Set
SIPEND[IRQ0]
Figure 11-9. IRQ0 Logical Representation
Chapter 11. System Interface Unit
Start
Bit Not Set in SIMASK
End
SIEL[ED0]
MUX
Level
Edge
Part III. Configuration
NMI
SIPEND[IRQ0]
11-15
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