Motorola MPC860 PowerQUICC User Manual page 977

VFLS0 ¥ 1
GND ¥ 3
GND ¥ 5
HRESET ¥ 7
V ¥ 9
DD
Figure 37-8. Development Port/BDM Connector Pinout Options
Internal freeze status can also be monitored through status in the data shifted out of the
debug port.
37.3.2.2 Development Port Registers
The development port consists logically of three registers:
¥ The trap enable control register (TECR)
¥ The development port instruction register (DPIR)
¥ Development port data register (DPDR)
DPIR and DPDR are both implemented as the development port shift register, which also
acts as a temporary holding register for data to be stored in the TECR.
37.3.2.2.1 Development Port Shift Register
Instructions and data are serially shifted into the 35-bit development port shift register from
the DSDI. DSCK or CLKOUT is the shift clock, depending on the debug port clock mode.
See Section 37.3.2.3, ÒDevelopment Port Serial CommunicationsÐClock Mode.Ó
The instructions or data are then transferred in parallel to the core and TECR. When the
processor enters debug mode it fetches instructions from DPIR that cause an access to the
development port shift register. These instructions are serially loaded into the shift register
from DSDI using DSCK or CLKOUT as the shift clock. Similarly, data is transferred to the
core. Data is shifted into the shift register and read by the processor by executing
mfspr[DPDR]. Data is also parallel loaded into the development port shift register from
the core by executing mtspr[DPDR]. It is then serially shifted out to DSDO using DSCK
or CLKOUT as the shift clock.
37.3.2.2.2 Trap Enable Control Register (TECR)
The TECR is a 9-bit register that is loaded from the development port shift register. The
contents of TECR drives the six trap enable signals, two breakpoint signals, and VSYNC
signal to the core. The transfer data to TECR commands send the appropriate bits to the
TECR. The TECR is not accessed by the core, but supplies signals to the core. The trap
enable bits, VSYNC bit, and the breakpoint bits of this register are loaded from the
development port shift register as the result of trap enable mode transmissions. The trap
enable bits are reßected in ICTRL and LCTRL2. Section 37.5.1.1, ÒComparator AÐH Value
Registers (CMPAÐCMPH),Ó describes support registers.
MOTOROLA
2 ¥ SRESET
4 ¥ DSCK
6 ¥ VFSL1
8 ¥ DSDI
10 ¥ DSDO
Chapter 37. System Development and Debugging
Part VI. Debug and Test
FRZ ¥ 1 2 ¥ SRESET
GND ¥ 3 4 ¥ DSCK
GND ¥ 5 6 ¥ FRZ
HRESET ¥ 7 8 ¥ DSDI
V ¥ 9 10 ¥ DSDO
DD
37-27