Motorola MPC860 PowerQUICC User Manual page 869

Table 33-6. PIPC Field Descriptions (Continued)
Bits Name
12Ð MODH Mode high. Determines the mode of the PIP upper 10 signals, PB[14Ð23], which comprise the 8-bit
13 PIP and its control signals. Can be modiÞed when the CP is not transferring data.
00 Port B general-purpose I/O (PIP disabled)
01 Transparent transfer modeÑcontrolled by the CP.
10 Interlocked handshake modeÑcontrolled by the CP or core.
11 Pulsed handshake modeÑcontrolled CP or core.
14 HSC Host control.
0 The CP controls transfers using PIP parameter RAM, buffer descriptors, and SDMA channels.
1 PIP data transfers are controlled by the core.
15 T/R Transmit/receive. Selects transmitter or receiver operation for the PIP.
0 Receive. Data is input to the PIP.
1 Transmit. Data is output from the PIP.
33.4.2 PIP Event Register (PIPE)
The PIP event (PIPE) register is used to generate interrupts and report events recognized by
the PIP controller. It shares the same address as the SMC2 event register, which cannot be
used at the same time as the PIP. Since PIP is not full duplex, the one PIPE register can
report both transmit and receive events concurrently.
When the PIP recognizes an event, it sets the corresponding event bit in the PIPE. PIPE
interrupts can be masked in the PIP mask register (PIPM). Writing ones to the PIPE bits
clears the events; writing zeros has no effect. All unmasked ßags must be cleared before the
CP clears internal interrupt requests. Figure 33-6 shows the register format.
Bit 0
Field
Reset
R/W
Addr
Table 33-7 describes PIPE Þelds.
Bits Name
0Ð2 Ñ Reserved. Should be cleared by writing ones.
3 TXE Transmit error. Indicates a general transmit errorÑthe source of the speciÞc error can be read in the
current buffer descriptorÕs status and control Þeld; see Section 33.5.1, ÒThe PIP Tx Buffer Descriptor
(TxBD).Ó
4 CCR Control character received. A control character was received and stored in the received control
character register (RCCR) in the PIP parameter RAM.
MOTOROLA
1 2
TXE
Ñ
Figure 33-6. PIP Event Register (PIPE)
Table 33-7. PIPE Field Descriptions
Chapter 33. Parallel Interface Port
Part V. The Communications Processor Module
Description
3 4
CCR BSY
0
R/W
0xA96
Description
5 6
RCH/TCH RXB/TXB
7
33-9