Motorola MPC860 PowerQUICC User Manual page 959

DEVELOPMENT
SYSTEM OR
EXTERNAL
PERIPHERALS
MASKABLE BREAKPOINT
DEVELOPMENT
NONMASKABLE BREAKPOINT
PORT
DEVELOPMENT PORT TRAP ENABLE BITS
SOFTWARE TRAP ENABLE BITS
LCTRL2
NONMASKED CONTROL BIT
MSR
MSR
INTERNAL
WATCHPOINTS
WATCHPOINTS
LOGIC
Figure 37-1. Watchpoints and Breakpoint Support in the Core
37.2.1 Key Features
The following list summarizes features of the internal watchpoints and breakpoints support.
¥ Four I-address comparators supporting equal, not equal, greater than, and less than.
¥ Two L-address comparators supporting equal, not equal, greater than, and less than.
Includes lsb masking, according to the size of the bus cycle for the byte and
half-word working modes. See Section 37.2.4.2, ÒByte and Half Word Working
Modes.Ó
¥ Two L-data comparators supporting equal, not equal, greater than, and less than.
Includes byte, half-word, and word operating modes, and four byte mask bits for
each comparator. It can be used for integer data. A match is detected only on the
valid part of the data bus (according to the cycleÕs size and the two address lsbs).
¥ No internal breakpoint/watchpoint support for unaligned words and half words.
¥ L-data comparators can be programmed to treat integers as signed or unsigned.
¥ Combined comparator pairs to detect in and out of range conditions, including either
signed or unsigned values on the L-data.
MOTOROLA
µ
CPM CODE
DEVELOPMENT
ACCESSIBLE
INTERNAL
PERIPHERALS
RI
Chapter 37. System Development and Debugging
Part VI. Debug and Test
X BIT WISE AND
X
BIT WISE OR
X
X
COUNTERS
BREAKPOINT
TO CPU
TO
WATCHPOINT
PINS
37-9