Motorola MPC860 PowerQUICC User Manual page 776

Part V. The Communications Processor Module
22. Clear P_PER. It is not used.
23. Clear IADDR1ÐIADDR4. The individual hash table is not used.
24. Clear TADDR_H, TADDR_M, and TADDR_L for clarity.
25. Initialize the RxBD and assume the Rx data buffer is at 0x0000_1000 in main
memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data
Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer].
26. Initialize the TxBD and assume the Tx data frame is at 0x0000_2000 in main
memory and contains fourteen 8-bit characters (destination and source addresses
plus the type Þeld). Write 0xFC00 to TxBD[Status and Control], add PAD to the
frame and generate a CRC. Then write 0x000D to TxBD[Data Length] and
0x0000_2000 to TxBD[Buffer Pointer].
27. Write 0xFFFF to the SCCE register to clear any previous events.
28. Write 0x001A to the SCCM register to enable the TXE, RXF, and TXB interrupts.
29. Write 0x4000_0000 to the CIMR so that SCC1 can generate a system interrupt. The
CICR register should also be initialized.
30. Write 0x0000_0000 to GSMR_H1 to enable normal operation of all modes.
31. Write 0x1088_000C to the GSMR_L1 register to conÞgure CTS (CLSN) and CD
(RENA) to automatically control transmission and reception (DIAG bits) and the
Ethernet mode. TCI is set to allow more setup time for the EEST to receive the
MPC860 transmit data. TPL and TPP are set for Ethernet requirements. The DPLL
is not used with Ethernet. Note that the ENT and ENR are not enabled yet.
32. Write 0xD555 to the DSR.
33. Set the PSMR1 to 0x0A0A to conÞgure 32-bit CRC, promiscuous mode, and begin
searching for the start frame delimiter 22 bits after RENA.
34. Enable the TENA pin (RTS). Since GSMR[MODE] are written to Ethernet, the
TENA signal is low. Set PCPAR[15] and clear PCDIR[15].
35. Write 0x1088_003C to GSMR_L1 to enable the SCC1 transmitter and receiver. This
additional write ensures that ENT and ENR are enabled last.
After 14 bytes and the 46 bytes of automatic pad (plus the 4 bytes of CRC) are sent, the
TxBD is closed. Additionally, the receive buffer is closed after a frame is received. Any data
received after 1520 bytes or a single frame causes a busy (out-of-buffers) condition because
only one RxBD is prepared.
28-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA